The internal registers contain 20a bits of readlwrite memory that are accessible to the programmer. These registers include two sets of six general-purpose registers which may be used individually as either a-bit registers or as 16-bit register pairs. In addition, there are two sets of accumulator and flag registers.

• THE INSTRUCTION SET CONTAINS 158 INSTRUCTIONS. THE 78 INSTRUCTIONS OF THE 8080A ARE INCLUDED AS A SUBSET; 8080A AND Z80 SOFTWARE COMPATIBILITY IS MAINTAINED

• THE CPU, RESULT IN RAPID INSTRUCTION EXECUTION WITH CONSEQUENT HIGH DATA THROUGHPUT

• THE EXTENSIVE INSTRUCTION SET INCLUDES STRING, BIT, BYTE, AND WORD OPERATIONS. BLOCK SEARCHES AND BLOCK TRANSFERS TOGETHER WITH INDEXED AND RELATIVE ADDRESSING RESULT IN THE MOST POWERFUL DATA HANDLING CAPABILITIES IN THE MICROCOMPUTER INDUSTRY

• THE Z80C MICROPROCESSORS AND ASSOCIATED FAMILY OF PERIPHERAL CONTROLLERS ARE LINKED BY A VECTORED INTERRUPT SYSTEM. THIS SYSTEM MAY BE DAISY-CHAINED TO ALLOW IMPLEMENTATION OF A PRIORITY INTERRUPT SCHEME. LITTLE, IF ANY, ADDITIONAL LOGIC IS REQUIRED FOR DAISY-CHAINING

• DUPLICATE SETS OF BOTH GENERAL-PURPOSE AND FLAG REGISTERS ARE PROVIDED, EASING THE DESIGN AND OPERATION OF SYSTEM SOFTWARE THROUGH SINGLE-CONTEXT SWITCHING, BACKGROUND-FOREGROUND PROGRAMMING, AND SINGLE-LEVEL INTERRUPT PROCESSING. IN ADDITION, TWO 16-BIT INDEX REGISTERS FACILITATE PROGRAM PROCESSING OF TABLES AND ARRAYS

• THERE ARE THREE MODES OF HIGH SPEED INTERRUPT PROCESSING: 8080 SIMILAR, NON-Z80 PERIPHERAL DEVICE, AND Z80 FAMILY PERIPHERAL WITH OR WITHOUT DAISY CHAIN

• ON-CHIP DYNAMIC MEMORY REFRESH COUNTER

• SINGLE 5 V ± 10 % POWER SUPPLY

• LOW POWER CONSUMPTION:
  - 9 mA TYP. AT 4 MHz
  - 15 mA TYP. AT 6 MHz
  - 20 mA TYP. AT 8 MHz
  - LESS THAN 10 mA IN POWER DOWN MODE